Physically-Based Methodology for the EMC-Compliant Design and Verification of Automotive System Ics

Description

In the recent decades, automotive electronics has undergone a rapid evolution towards highly complex multifunction chips. So-called Automotive System ICs can integrate multiple DC/DC-converters, a logic core, linear regulators, smart switches, sensor interfaces and transceivers on a single die. If electromagnetic compatibility (EMC) issues are discovered late, the complex investigations and the required rework can significantly prolong the time-to-market. Moreover, if the EMC is already improved on the chip level, less effort is required to achieve electromagnetic compatibility. The methodology developed in this thesis employs novel physically-based modeling techniques for IC-package and substrate parasitics. Furthermore, the modeling of inductances and RF-losses in on-die power routing were advanced in a proprietary BCD-technology. The presented modeling techniques cope with the accuracy requirements of EMC-simulations.

The requirements on IC-package models for the use in EMC-simulations go far beyond what is typically used in function verification. Mutual pin-loop inductances of three orders of magnitude below typical pin-inductances can already cause non-compliance with the EMC-requirements. It will be shown that, if magnetic shielding by the PCB-ground plane is neglected, errors in the predicted RF-emissions of the DC/DC-converter can be up to 19 dB. The presented novel approach can take a large number of small mutual pin-loop inductances into account at a high accuracy. In this thesis, the inductances as well as the inductive RF-losses in the power routing will be quantified experimentally and reproduced by means of field simulation and parasitic extraction. In future high-frequency extensions of DPI-testing, internal resonances, the quality factor of which depends on the RF-losses, may increase in relevance. It was demonstrated how eddy-current losses in the metallization can be exploited to dampen these resonances.

Furthermore, in this thesis, a flexible substrate extraction tool is developed. It is distinguished by the fact that the precise semantics of the field model are transparent and available to the user. Moreover, a novel marker layer concept helps to precisely configure the model’s level of detail. This marker layer concept and a novel ₃D mesh compression technique (S-EHRFEM) helps to drastically reduce the simulator run time.

The developed test-IC contains a DC/DC-converter running at 3 MHz and a digital disturber clocked at 32 MHz, both of which can act as disturbance sources. The RF-emissions are evaluated at three different transceiver pins, in each case in the recessive and dominant bus state. In the complete frequency range from 3 MHz to 1 GHz, the simulations achieve a good accuracy in the prediction of the DC/DC’s RF-emissions, with deviations typically less than ±6 dB. The involved RF-coupling mechanisms are analyzed in detail. These discussions are enabled by an automated simplification using sensitivity analyses, and are based on low-dimensional substrate models, in which the n-buried layer is approximated as equipotential. Furthermore, various counteractive measures are tested and discussed. For example, it was experimentally verified that separating the digital from the system ground is highly effective, and can achieve reductions of 31 dB at 50 MHz and 15 dB at 300 MHz.